PHYSICAL DESIGN

  PD FLOW

1.  partitioning
2. floorplan
3. powerplan
4. placement
5. clock tree synthesis
6. routing 

PD INPUTS

 In VLSI physical design, the process starts with several key inputs that guide the layout and implementation of the design. These inputs ensure that the final chip meets performance, power, and area (PPA) constraints. Below are the primary inputs for physical design:

1. Netlist

• Definition: A representation of the circuit consisting of logic gates and their interconnections.
• Format: Typically provided in Verilog or VHDL format.
• Source: Comes from the synthesis process after logic design.

2. Technology File

• Definition: Contains the design rules and technology constraints specific to the fabrication process.
• Contents:
  • Metal layer specifications
  • Routing rules (min width, spacing)
  • Cell dimensions
  • DRC (Design Rule Constraints)
• Provided by: Foundry (TSMC, Intel, GlobalFoundries, etc.).

3. Standard Cell Library (STD Cell)

• Definition: A set of pre-designed and pre-verified logic gates like NAND, NOR, Flip-Flops, etc.
• Includes:
  • LEF (Library Exchange Format): Contains abstract physical views (shape, pin locations).
  • LIB (Library File): Defines cell timing, power, and functionality.
  • GDSII: Provides detailed layout information.

4. Timing Constraints (SDC File)

• Definition: Specifies the timing requirements of the design using Synopsys Design Constraints (SDC).
• Includes:
  • Clock definitions (clock period, skew, uncertainty)
  • Input/output delays
  • Multicycle and false paths
  • Setup and hold constraints

5. Power Intent File (UPF/CPF)

• Definition: Defines the power management strategy, including power domains and voltage levels.
• Formats: Unified Power Format (UPF) or Common Power Format (CPF).
• Includes:
  • Power domains (ON/OFF states)
  • Voltage islands
  • Power switches and retention cells

6. Design Floorplan

• Definition: Specifies the chip size, block placement, IO pads, and power grid structure.
• Includes:
  • Core area and aspect ratio
  • Macro placements (Memories, PLLs, etc.)
  • Power grid design (VDD/VSS rails)

7. Physical Verification Rule Decks

• Definition: Files required for Design Rule Check (DRC) and Layout vs. Schematic (LVS) verification.
• Formats: Provided in Calibre (Mentor) or IC Validator (Synopsys).
• Includes:
  • DRC rules (metal width, spacing, via rules)
  • LVS rules (netlist vs. layout consistency)

8. Parasitic Extraction Files

• Definition: Contains information on how parasitics (capacitance, resistance) impact timing.
• Formats: SPEF (Standard Parasitic Exchange Format) or RSPF.
• Used for: Static Timing Analysis (STA) and Signal Integrity analysis.