Placement in VLSI Physical Design
1. What is Placement?
Placement is the process of positioning standard cells and macros within the floorplan while optimizing for timing, power, and congestion. It ensures that:
- Cells are placed legally (without overlap).
- The design meets timing constraints.
- Congestion and routing complexity are minimized.
2. Goals of Placement
The key objectives of placement are:
1. Legal Cell Placement
- Standard cells and macros must be placed without overlapping.
- Must follow design rules (cell row alignment, spacing, etc.).
2. Optimize Wirelength
- Shorter interconnects reduce parasitic delays and improve timing.
- Reduces power consumption by minimizing unnecessary switching activity.
3. Timing Optimization (Setup & Hold)
- Reduce critical path delay by placing frequently communicating cells closer.
- Avoid excessive clock tree insertion delay (clock aware placement).
4. Congestion Reduction
- Avoid placing too many high-connectivity cells in one region.
- Prevent routing congestion that can lead to Design Rule Violations (DRC).
5. Power Distribution
- Ensure balanced power dissipation across the chip.
- Reduce IR drop by avoiding excessive power-demanding cells in one area.
6. Signal Integrity & Crosstalk Minimization
- Avoid placing high-speed signals in parallel for long distances.
- Shield critical signals using power/ground tracks.
3. Stages of Placement
Placement occurs in multiple steps:
Pre-Placement (Initial Placement)
- Cells are roughly placed based on netlist connectivity.
- No timing or congestion optimization yet.
Global Placement
- Optimizes overall wirelength while keeping timing in check.
- Focuses on macro and standard cell spreading.
- Doesn't consider detailed legal positioning yet.
Legalization
- Adjusts cell positions to follow legal design rules.
- Ensures no cell overlaps and maintains row alignment.
Detailed Placement
- Fine-tunes placement for better timing and congestion handling.
- Considers clock tree synthesis (CTS) effects.
- Balances cell density to avoid hotspots.
4. Placement Constraints & Considerations
To ensure an optimal placement, several constraints must be followed:
1. Cell Density Control
- Avoid highly packed areas that can cause routing congestion.
- Use cell spreading techniques to maintain uniform distribution.
2. Macro Placement Guidelines
- Place macros near the periphery to reduce congestion.
- Keep macro pins aligned for easier routing.
- Avoid blocking critical signal paths.
3. Timing-Driven Placement
- Ensure setup and hold timing constraints are met.
- Reduce clock-to-Q and data path delays.
4. Power-Aware Placement
- High-power blocks should be distributed evenly.
- Avoid clustering high-switching cells to reduce IR drop.
5. Avoid High Fanout Net Issues
- Buffer high fanout nets to maintain signal integrity.
- Distribute loads efficiently across the design.
5. Placement Verification & Optimization
Once placement is complete, verification and optimizations are performed:
📌 Congestion Analysis → Check if routing channels are over-utilized.
📌 Timing Analysis (STA) → Ensure setup and hold timing are met.
📌 IR Drop Analysis → Verify power grid stability.
📌 Crosstalk Analysis → Reduce unwanted noise between signals.
6. Tools Used for Placement
Common EDA tools used for placement in VLSI:
- Cadence Innovus
- Synopsys ICC2 (IC Compiler II)
- Mentor Graphics Olympus-SoC