Engineering Change Order (ECO) in VLSI Physical Design

1. What is an ECO?

An Engineering Change Order (ECO) is a modification to an existing design at any stage of the VLSI design flow, typically after synthesis, placement, or routing. ECOs are used to fix functional bugs, timing violations, or design changes without restarting the entire design process.

Goal: Implement changes efficiently without redoing the entire design to save time and effort.

2. Types of ECOs in Physical Design

Functional ECO

🔹 Purpose: Fix logical errors after synthesis.
🔹 Example: Change a combinational logic gate, update a flip-flop, or modify a multiplexer.
🔹 Fix: Modify netlist connections without re-synthesizing the entire design.

Timing ECO

🔹 Purpose: Fix setup or hold violations after placement and routing.
🔹 Example: A data path is too slow, causing setup violations at high frequency.
🔹 Fix:
✔ Resize cells (use stronger buffers or logic gates).
✔ Insert buffers to fix hold violations.
✔ Change clock tree buffers if needed.

Power ECO

🔹 Purpose: Optimize power consumption without affecting functionality.
🔹 Example: Reduce dynamic power by replacing high-power gates with low-power equivalents.
🔹 Fix:
✔ Use multi-Vt cells (replace high-power gates with low-Vt alternatives).
✔ Reduce clock switching activity by gating unnecessary clock signals.

Metal-Only ECO

🔹 Purpose: Implement small fixes without modifying the base layers (diffusion, polysilicon).
🔹 Example: Change connections by modifying only metal layers.
🔹 Fix:
✔ Modify only routing layers (M1, M2, M3, etc.) to avoid major rework.
✔ Reduce turnaround time by avoiding changes in standard cells.

3. ECO Implementation Flow

Step 1: Identify the issue (functional bug, timing violation, etc.).
Step 2: Generate an ECO netlist with required changes.
Step 3: Apply the changes in the design tool (ICC, Innovus, or Fusion Compiler).
Step 4: Perform incremental placement, CTS, and routing to update changes.
Step 5: Run STA, LVS, and DRC checks to validate correctness.

4. Tools Used for ECO

🔹 Synopsys Design Compiler (DC) – For logic ECOs.
🔹 Cadence Genus & Innovus – For placement & timing ECOs.
🔹 Synopsys ICC2/Fusion Compiler – For physical ECOs.
🔹 Calibre (Siemens) – For DRC & LVS verification after ECO.