Layout vs. Schematic (LVS) in VLSI Physical Design
1. What is LVS?
Layout vs. Schematic (LVS) is a verification process that ensures the physical layout matches the logical schematic before fabrication. It checks whether the connectivity and components in the layout correspond correctly to the schematic.
Goal: Ensure that the circuit functionality is preserved from schematic to layout, preventing costly errors in fabrication.
2. Why is LVS Important?
✔ Prevents functional mismatches between schematic and layout.
✔ Ensures correct connectivity (no missing or extra components).
✔ Avoids fabrication errors that can cause chip failure.
✔ Saves time and cost by catching errors early.
3. LVS Flow (Steps in LVS Check)
LVS is performed in the following steps:
1️⃣ Extract Netlist from Layout
- The physical layout is converted into a netlist (list of devices & connections).
- The extracted netlist is compared with the schematic netlist.
2️⃣ Compare Layout Netlist with Schematic Netlist
- LVS tool compares both netlists and reports:
- Match → Layout and schematic are identical ✅
- Mismatch → Errors found ❌
3️⃣ Debug LVS Errors
- If mismatches are found, they are categorized as:
🔹 Device Mismatch → Missing or extra transistors, resistors, or capacitors.
🔹 Net Mismatch → Incorrect wiring between components.
🔹 Parameter Mismatch → Transistor width/length is incorrect.
4️⃣ Fix LVS Violations & Rerun LVS
- Modify the layout to correct errors.
- Rerun LVS until it is LVS-clean.
4. Common LVS Errors & Fixes
| LVS Error | Cause | Solution |
|---|---|---|
| Missing Device | Transistor, capacitor, or resistor missing in layout | Add missing device |
| Extra Device | Extra component added in layout | Remove extra device |
| Short Circuit | Two nets are unintentionally connected | Fix routing |
| Open Circuit | A net is disconnected or floating | Ensure proper connections |
| Mismatch in Transistor Parameters | Incorrect W/L ratio in layout | Correct transistor sizing |
| Pin Mismatch | Pins in layout do not match schematic | Assign correct pin names |
5. LVS Verification Tools
🔹 Calibre LVS (Siemens/Mentor Graphics)
🔹 IC Validator (Synopsys)
🔹 Assura LVS (Cadence)
🔹 PVS LVS (Cadence)