Pulse Width Violation (PWD)

 

Pulse Width Violation in VLSI Design

1. What is a Pulse Width Violation?

A Pulse Width Violation occurs when the low phase or high phase of a clock signal is too short. This can cause setup and hold time violations, leading to incorrect circuit operation.

📌 Key Issue: If the pulse width is too short, flip-flops and other sequential elements may not capture data correctly.

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2. Causes of Pulse Width Violations

🔹 Unequal duty cycle: If the clock high and low times are not balanced, it can cause instability.
🔹 Clock tree imbalance: Incorrect buffering and skew in the clock tree synthesis (CTS) stage.
🔹 Clock jitter: Variations in clock signal timing due to noise.
🔹 Process variations: Differences in transistor speeds due to fabrication.
🔹 Incorrect constraints: Wrong clock definitions in timing constraints (SDC file).

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3. Effects of Pulse Width Violations

❌ Setup & hold violations: Data may not be latched correctly.
❌ Metastability: Flip-flops may enter an unpredictable state.
❌ Functional failure: The circuit may not operate at the intended frequency.
❌ Clock glitches: Can cause incorrect toggling of sequential elements.

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4. How to Fix Pulse Width Violations?

1. Adjust Duty Cycle

• Ensure a 50% duty cycle by modifying clock definitions in the SDC file.
• Example:

  create_clock -name CLK -period 2ns -waveform {0 1}
  

  (This defines a clock with a 50% duty cycle: High for 1ns, Low for 1ns.)

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2. Improve Clock Tree Balancing

• During Clock Tree Synthesis (CTS), ensure balanced buffering of clock branches.
• Use additional buffers to equalize delays.

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3. Reduce Clock Jitter

• Use low-noise power delivery and ensure proper grounding.
• Select a high-quality clock source.

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4. Modify Timing Constraints

• Define min/max pulse width constraints in the Static Timing Analysis (STA) tool.
• Example constraint for Synopsys PrimeTime:

  set_min_pulse_width -high 0.8 [get_clocks CLK]
  set_min_pulse_width -low 0.8 [get_clocks CLK]
  

  (Ensures that both high and low pulses are at least 0.8ns.)

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5. Increase Drive Strength

• Use stronger clock buffers to maintain signal integrity.
• Reduce the number of fan-out loads on the clock path.

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5. Pulse Width Check in STA

• Tools like Synopsys PrimeTime, Cadence Tempus, and Siemens/Mentor Calibre perform pulse width checks as part of Static Timing Analysis (STA).
• The tool reports pulse width violations, which must be debugged and fixed before tape-out.