Design Rule Check (DRC) in VLSI Physical Design
1. What is DRC?
Design Rule Check (DRC) is a physical verification process that ensures the layout follows the foundry-defined design rules for manufacturability. These rules define the minimum width, spacing, via enclosures, and other geometric constraints to prevent fabrication defects.
Goal: Ensure that the layout is manufacturable and error-free, preventing yield loss and chip failures.
2. Why is DRC Important?
✔ Ensures the design meets fabrication constraints.
✔ Prevents short circuits, open circuits, and yield loss.
✔ Ensures higher reliability and better performance.
✔ Helps achieve a DRC-clean layout, avoiding costly silicon failures.
3. Common DRC Rules
✅ 1. Width Rules
- Defines minimum width for metals, poly, diffusion, etc.
- Ensures wires are not too thin, preventing high resistance and breaks.
Example: Minimum metal width = 0.07µm
✅ 2. Spacing Rules
- Defines minimum spacing between two metal layers to avoid shorts.
- Helps reduce crosstalk and noise.
Example: Minimum spacing between metal lines = 0.08µm
✅ 3. Via & Contact Rules
- Ensures vias are large enough and correctly enclosed by metal layers.
- Prevents high resistance, electromigration, and open circuits.
Example:
✔ Via enclosure rule: Via must be enclosed by metal on all sides by 0.02µm
✅ 4. Overlap & Extension Rules
- Ensures proper overlap between layers to avoid open circuits.
- Prevents alignment errors during manufacturing.
Example:
✔ Poly must extend over active diffusion by 0.05µm
✅ 5. Density Rules (CMP Check)
- Ensures uniform metal density to avoid dishing or erosion during Chemical Mechanical Polishing (CMP).
- Uses dummy metal fill to balance density.
Example: Minimum metal density in any region must be > 30%
✅ 6. Antenna Rules
- Checks for antenna effect, which can damage transistors during fabrication.
- Prevents excessive charge buildup on long interconnects.
Solution: Use antenna diodes or metal jumpers to higher layers.
4. DRC Flow (Step-by-Step Process)
Step 1: Run DRC tool (Calibre, IC Validator, Assura).
Step 2: Identify violations (errors in spacing, width, etc.).
Step 3: Debug and fix errors in the layout.
Step 4: Rerun DRC until the design is DRC-clean.
5. DRC Errors & Fixes
| DRC Error | Cause | Solution |
|---|---|---|
| Width Violation | Metal/poly/diffusion too narrow | Increase width |
| Spacing Violation | Two metals too close | Increase spacing |
| Via Enclosure Violation | Via not enclosed properly | Adjust via enclosure |
| Antenna Violation | Long metal paths causing charge buildup | Add antenna diode |
| Density Violation | Uneven metal distribution | Add dummy metal fills |
6. DRC Verification Tools
🔹 Calibre DRC (Siemens/Mentor Graphics)
🔹 IC Validator (Synopsys)
🔹 Assura DRC (Cadence)
🔹 PVS DRC (Cadence)