Synthesis Fixes & Optimization Techniques in Physical Design

🔹 What is Synthesis?

Synthesis converts RTL (Verilog/VHDL) into gate-level netlist, optimizing for timing, area, and power. Key techniques help fix common issues like timing violations, high area, and power consumption.

Fixes & Optimization Techniques in Synthesis

1️⃣ Timing Optimization Techniques

Timing closure requires fixing setup and hold violations.

Setup Violation Fixes (Reduce Path Delay)

Logic Restructuring: Reduce logic depth.
Pipelining: Add registers to break long combinational paths.
Cell Upsizing: Replace slower cells with faster ones.
Retiming: Move registers across logic to balance delay.

Example (Synopsys DC Command for Timing Optimization)

set_max_delay 2.0 -from REG1 -to REG2
compile -timing

Hold Violation Fixes (Increase Data Path Delay)

Buffer Insertion: Add delay buffers.
Cell Downsizing: Use slower cells to delay signal propagation.
Routing Detour: Increase path length artificially.

Example (Fix Hold Timing in Synopsys DC)

set_fix_hold [all_clocks] -max_delay 0.1

2️⃣ Area Optimization Techniques

Reducing gate count helps minimize area without affecting performance.

Techniques to Reduce Area

Logic Sharing: Merge duplicate logic.
Resource Sharing: Use multiplexers instead of separate units.
Reduce Fanout: Limit the number of loads per cell.
Use Multi-bit Flip-Flops (MBFFs): Reduces cell count.

Example (Minimize Area in Synopsys DC)

set_max_area 50000
compile -area

3️⃣ Power Optimization Techniques

Reducing dynamic and leakage power is crucial for low-power design.

Dynamic Power Optimization (Reduces Switching Activity)

Clock Gating: Turns off clocks when not needed.
Data Gating: Blocks unnecessary data transitions.

Example (Clock Gating in Synopsys DC)

set_clock_gating_style -sequential_cell DFF -control_signal EN
compile -power

Leakage Power Optimization (Reduces Static Power Consumption)

Use Low-Vt Cells: Lower leakage transistors.
Power Gating: Turn off power to unused blocks.

Example (Power Gating with UPF in DC)

create_power_domain PD_BLOCK -elements {u_block}
set_retention PD_BLOCK -retention_signal RET_EN -retention_supply VDD_RET

4️⃣ Clock Tree Optimization Techniques

A well-balanced Clock Tree Synthesis (CTS) reduces skew and latency.

Clock Skew Reduction

Use Clock Buffers: Distribute clock uniformly.
Balancing Clock Paths: Equalize delays across flops.

Example (Max Skew Constraint in DC)

set_clock_uncertainty 0.2 [get_clocks clk]

Clock Latency Reduction

Place Clock Sources Close to Sinks.
Reduce Number of Buffers in the path.

5️⃣ Latch & FSM Optimization Techniques

Avoid unwanted latches and improve FSM efficiency.

Latch Removal

Ensure every variable has a default assignment.
Use synchronous always blocks for sequential logic.

Example (Avoid Latches in Verilog)

always @(*) begin
    if (en)
        out = data;
    else
        out = 0;  // Ensure default assignment
end

FSM Optimization

One-Hot Encoding for speed.
Binary Encoding for area.
Gray Encoding for low power.

Example (FSM Optimization in DC)

set_fsm_encoding style onehot
compile

Summary of Key Synthesis Fixes

Issue	Fixes & Techniques
Setup Violations	Pipelining, cell upsizing, retiming
Hold Violations	Buffer insertion, cell downsizing
High Area	Logic sharing, multi-bit flip-flops (MBFF)
High Power	Clock gating, power gating, low-Vt cells
Clock Skew	Balanced CTS, clock buffer insertion
Unintended Latches	Use proper sensitivity list in RTL
FSM Optimization	One-hot encoding for speed, Gray for low power

Key Commands for Synthesis in Synopsys Design Compiler

Optimization	Command
Timing Optimization	`compile -timing`
Area Optimization	`compile -area`
Power Optimization	`compile -power`
Clock Gating	`set_clock_gating_style`
FSM Encoding	`set_fsm_encoding`
Fix Hold Violations	`set_fix_hold`