Goals and Requirements of Floorplanning in Physical Design
1. What is Floorplanning?
Floorplanning is the first step in physical design where the chip layout is planned by determining the placement of standard cells, macros, and I/O pads while optimizing for performance, power, and area (PPA).
Goals of Floorplanning
The primary objectives of floorplanning are:
✅ 1. Minimize Wirelength
- Reducing the total interconnect length improves timing and power efficiency.
- Shorter wires reduce delay and IR drop.
✅ 2. Optimize Placement of Macros & Standard Cells
- Ensure efficient utilization of area by placing macros and standard cells optimally.
- Prevent congestion in routing.
✅ 3. Reduce Congestion
- Avoid too many connections in a small region.
- Balanced routing resources lead to better signal integrity.
✅ 4. Optimize Timing (Setup & Hold)
- Reduce critical path delay by placing frequently interacting components closer.
- Ensure clock tree has balanced paths to prevent skew.
✅ 5. Ensure Proper Power Planning
- Design power grid for stable voltage distribution.
- Minimize IR drop and electromigration (EM) issues.
✅ 6. Provide Space for Routing
- Avoid macro placements that block routing channels.
- Ensure sufficient via access for interconnects.
✅ 7. Consider DFM (Design for Manufacturability)
- Follow foundry guidelines to ensure ease of manufacturing.
- Reduce yield loss due to design rule violations.
Requirements for Floorplanning
To achieve the above goals, certain requirements must be met:
1. Design Specifications
- Technology node (e.g., 5nm, 7nm)
- Die size & aspect ratio
- Power & Performance constraints
2. Inputs for Floorplanning
- Netlist (from synthesis)
- Standard Cell Library (LEF, LIB, GDSII)
- Macro & IP blocks (SRAM, PLL, ADC, etc.)
- Timing Constraints (SDC file)
- Power Intent (UPF/CPF)
3. Design Considerations
✅ Aspect Ratio: Maintain a balanced core-to-die ratio.
✅ Keep Macros on the Periphery: Large blocks like SRAM, PLLs should be placed near the edges to reduce congestion.
✅ Align Pins for Easy Routing: Align macro pins to simplify interconnect routing.
✅ Avoid Hotspots: Prevent placing high-activity blocks near each other to reduce thermal issues.