Design Rule Violations (DRV) in Physical Design: Types and Fixes

1. What are DRV Violations?

Design Rule Violations (DRV) occur when the physical design does not meet certain electrical or routing constraints. These violations can lead to timing failures, power integrity issues, and manufacturability problems.

Goal: Identify and fix DRVs to ensure a reliable and high-performance chip.

2. Types of DRV Violations and Their Fixes

1️⃣ Short Violations

🔹 Cause: Two or more nets unintentionally connected, leading to a short circuit.
🔹 Fix:
✔ Check and adjust routing to remove unintended connections.
✔ Use Metal Fill/Spacing Rules to avoid shorts.

2️⃣ Open Violations

🔹 Cause: A net or signal is not connected properly, leading to an open circuit.
🔹 Fix:
✔ Identify missing connections using LVS and DRC checks.
✔ Ensure proper pin-to-pin connectivity.

3️⃣ Min Width Violations

🔹 Cause: A metal wire is narrower than the minimum width defined by DRC.
🔹 Fix:
✔ Increase wire width to meet DRC rules.
✔ Use metal layer optimization to improve width.

4️⃣ Min Area Violations

🔹 Cause: A metal shape is smaller than the allowed minimum area, leading to weak connections.
🔹 Fix:
✔ Increase the area of small metal polygons to avoid weak spots.
✔ Use dummy metal fills if necessary.

5️⃣ High Fanout Net Violations

🔹 Cause: A single net drives too many loads, causing timing and signal integrity issues.
🔹 Fix:
✔ Use buffer insertion to reduce fanout load.
✔ Apply cloning to duplicate drivers for better load balancing.

6️⃣ Max Transition Violations

🔹 Cause: Signal transition time (slew rate) is too high, leading to timing issues.
🔹 Fix:
✔ Insert buffers to strengthen weak signals.
✔ Optimize cell sizing for better drive strength.

7️⃣ Max Capacitance Violations

🔹 Cause: Excessive capacitive loading on a net, affecting timing and power.
🔹 Fix:
✔ Use buffering and driver resizing to reduce capacitance.
✔ Optimize routing to minimize unnecessary wire length.

8️⃣ Max Resistance Violations

🔹 Cause: Thin or long interconnects increase resistance, leading to delay and IR drop issues.
🔹 Fix:
✔ Use wider metal layers or multiple vias to reduce resistance.
✔ Improve routing to avoid long high-resistance paths.

9️⃣ Electromigration (EM) Violations

🔹 Cause: High current density causes metal degradation, leading to failure over time.
🔹 Fix:
✔ Increase wire width to handle more current.
✔ Use double via insertion to improve reliability.

3. DRV Analysis and Debugging Flow

Step 1: Run physical verification tools (Calibre, IC Validator, PVS).
Step 2: Identify DRV reports and categorize violations.
Step 3: Fix major violations (shorts, opens, width, and fanout issues).
Step 4: Optimize timing and routing for capacitance, transition, and resistance issues.
Step 5: Rerun DRV checks until the layout is DRV-clean.

4. Tools Used for DRV Checks

🔹 Calibre (Siemens/Mentor Graphics)
🔹 IC Validator (Synopsys)
🔹 PVS (Cadence)