PD FLOW
- partitioning: Dividing into smaller blocks and IP based on their usage and communications
- floorplan: Creation of die/core areas, port placement, macro placement, voltage areas, etc..
- powerplan: creation of power mesh and standard cells rails
- placement: placement of standard cells based on their connectivity, scan chain reordering, logic optimization
- clock tree synthesis: building of clock tree from clock port to clock sinks, optimizing the clock path to archive low latency and skew
- routing :routing of signal nets ,fixing drv &drcs, fixing signal integrity issues(crosstalk)
- STA: Analyzing the timing paths(setup,hold,transition..etc.) based on all scenarios
- signoff: Done verification on routed DB like LVS ,DRC,LEC,DFM,ERC,PERC,EMIR,etc.
- Tapeout: Final stage of verification in all aspects
- fabrication
- testing
- packaging