Placement Optimization Techniques for Reducing Timing and Congestion in Physical Design
1. Introduction
Placement plays a crucial role in timing, congestion, and overall performance of the design. Poor placement can cause setup and hold violations, routing congestion, and increased power consumption.
Goal: Optimize placement using floorplan-aware techniques and tool commands to improve timing, congestion, and power.
2. Key Placement Optimization Techniques
1️⃣ Congestion-Aware Placement
🔹 Why? Congested areas lead to routing detours, increasing wire length and resistance.
🔹 Fix:
✔ Spread cells evenly to avoid hotspots.
✔ Use placement blockages in high-density regions.
Command Example (Cadence Innovus):
setPlaceMode -congEffort high
place_design
analyze_congestion
(Sets high congestion effort during placement and analyzes congestion after placement.)
2️⃣ Timing-Driven Placement
🔹 Why? Poor placement of setup-critical paths increases delay, causing setup violations.
🔹 Fix:
✔ Place high-fanout cells close to their loads.
✔ Prioritize critical paths using tool settings.
Command Example (Synopsys ICC2):
set_place_opt -timing_driven true
place_opt
report_timing
(Enables timing-driven placement, optimizes, and checks violations.)
3️⃣ High-Fanout Net Optimization
🔹 Why? High fanout causes high capacitance, leading to longer delays.
🔹 Fix:
✔ Insert buffering to reduce fanout load.
✔ Clone high-fanout drivers for better timing.
Command Example (Synopsys ICC2):
setOptMode -fixHighFanout true
optDesign -preCTS
(Fixes high-fanout nets before clock tree synthesis (CTS).)
4️⃣ Cell Spreading to Reduce Density
🔹 Why? High cell density areas cause congestion and IR drop issues.
🔹 Fix:
✔ Spread cells apart to improve routing and power integrity.
Command Example (Cadence Innovus):
setPlaceMode -density 70
place_design
(Limits placement density to 70% to reduce congestion.)
5️⃣ Macro Placement Optimization
🔹 Why? Poor macro placement causes routing congestion and timing issues.
🔹 Fix:
✔ Align macros along the edges to allow better routing channels.
✔ Avoid macro clustering to prevent routing bottlenecks.
Command Example (Cadence Innovus - Macro Guidelines):
place_instance U1 -coordinate {100 200}
place_instance U2 -coordinate {300 400}
(Places macros at specific locations to avoid congestion.)
6️⃣ Wirelength Reduction for Better Timing
🔹 Why? Long wires increase RC delay, affecting setup timing.
🔹 Fix:
✔ Optimize cell locations to minimize net wirelength.
✔ Use global and detailed placement refinements.
Command Example (Synopsys ICC2):
setOptMode -wirelengthEffort high
optDesign -postPlace
(Reduces wirelength after placement to improve timing.)
3. Placement Optimization Flow
Step 1: Pre-placement analysis (floorplan, congestion map, timing paths).
Step 2: Enable congestion-driven and timing-aware placement.
Step 3: Adjust macro locations and cell density.
Step 4: Optimize high-fanout nets and long wire paths.
Step 5: Perform post-placement optimization (cell spreading, buffering, wirelength reduction).
Step 6: Validate timing and congestion reports.