PHYSICAL VERIFICATION

Physical Verification & Checks in VLSI

1. What is Physical Verification?

Physical Verification (PV) is the process of ensuring that the final layout of a chip adheres to manufacturing and design constraints before fabrication. It ensures that the design is:
✔ Error-free
✔ Meets foundry requirements
✔ Optimized for performance, power, and area (PPA)

📌 Goal: Ensure that the design is manufacturable and meets functional & electrical specifications.

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2. Key Physical Verification Checks

Physical verification consists of several essential checks:

✅ 1. Design Rule Check (DRC)

• Ensures that the layout follows foundry-specific rules.
• Checks for issues like:
  🔹 Minimum spacing between metals
  🔹 Minimum width of interconnects
  🔹 Via enclosure rules
  🔹 Antenna violations

Tool Used: Calibre DRC, IC Validator (ICV), Assura

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✅ 2. Layout vs. Schematic (LVS) Check

• Compares the layout with the schematic netlist to verify connectivity.
• Ensures no missing or extra components in the layout.
• Checks:
  🔹 Device matching (Transistors, resistors, capacitors)
  🔹 Netlist comparison
  🔹 Shorts & opens detection

Tool Used: Calibre LVS, PVS, Assura LVS

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✅ 3. Electrical Rule Check (ERC)

• Ensures electrical correctness of the design.
• Checks:
  🔹 Floating nodes (unconnected gates or outputs)
  🔹 Power/Ground shorts
  🔹 Unintended high-current paths

Tool Used: Calibre ERC, PVS, Assura ERC

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✅ 4. Antenna Rule Check (ARC)

• Checks antenna effects during fabrication (charge accumulation on long interconnects).
• Prevents damage to thin-oxide transistors.
• Fixes:
  🔹 Antenna diodes
  🔹 Metal jumpers to higher layers

Tool Used: Calibre, ICV, Assura

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✅ 5. Density Check (CMP & Metal Fill Analysis)

• Ensures uniform metal density to prevent Chemical-Mechanical Polishing (CMP) issues.
• Adds dummy metal fills to balance density.
• Prevents issues like:
  🔹 Dishing (over-polishing in low-density areas)
  🔹 Erosion (under-polishing in high-density areas)

Tool Used: Calibre CMP, Pegasus CMP

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✅ 6. IR Drop & Electromigration (EM) Check

• IR Drop Analysis: Ensures that power delivery is stable across the chip.
• Electromigration (EM) Check: Ensures metal interconnects can handle current density without degradation.
• Fixes:
  🔹 Widening power rails
  🔹 Adding redundant vias
  🔹 Optimizing power grid

Tool Used: Redhawk, Voltus, Totem

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✅ 7. Parasitic Extraction (PEX) & Post-Layout Simulation

• Extracts RC parasitics from the layout and creates an SPEF file.
• Used for Static Timing Analysis (STA) to check timing closure.
• Helps in post-layout simulation for accurate results.

Tool Used: StarRC, QRC, Calibre xACT, ICV PEX

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3. Physical Verification Flow

📌 Step 1 → Run DRC to check for design rule violations.
📌 Step 2 → Run LVS to verify netlist consistency.
📌 Step 3 → Perform ERC and Antenna Check.
📌 Step 4 → Conduct IR Drop & EM Analysis for power integrity.
📌 Step 5 → Extract parasitics (PEX) for post-layout STA.
📌 Step 6 → Perform CMP and metal fill analysis.
📌 Step 7 → Fix violations and rerun checks until the design is signoff clean.

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4. Tools Used in Physical Verification

💻 Calibre (Mentor/Siemens) → DRC, LVS, ERC, CMP, PEX
💻 IC Validator (Synopsys) → DRC, LVS, Antenna Check
💻 Assura (Cadence) → DRC, LVS
💻 Redhawk, Voltus → IR Drop & EM Analysis
💻 StarRC, QRC → Parasitic Extraction