Routing in VLSI Physical Design

1. What is Routing?

Routing is the process of connecting all the standard cells, macros, and I/O pins using metal interconnects while following design rules. It ensures that the physical connections match the logical netlist from synthesis.

📌 Goal: Establish proper connectivity while optimizing for timing, congestion, power, and manufacturability.

2. Goals of Routing

The main objectives of routing are:

✅ 1. Ensure Complete Connectivity

All nets must be correctly routed as per the netlist.
Avoid floating signals and open circuits.

✅ 2. Minimize Wirelength

Shorter wirelength reduces resistance (R), capacitance (C), and delay.
Improves timing and reduces dynamic power.

✅ 3. Reduce Congestion

Avoid high-density routing areas that can cause DRC (Design Rule Check) violations.
Maintain balanced routing utilization across the die.

✅ 4. Optimize Timing (Setup & Hold)

Minimize wire delay and crosstalk noise.
Ensure signal integrity for high-speed designs.

✅ 5. Reduce IR Drop & Electromigration (EM)

Use proper power routing (VDD/VSS) to maintain stable voltage.
Avoid excessive current density in narrow wires.

✅ 6. Meet Foundry Design Rules (DRC Clean)

Ensure correct metal spacing, via density, and layer usage.
Follow manufacturability guidelines to improve yield.

3. Types of Routing

Routing is done in two main stages: Global Routing and Detailed Routing.

1️⃣ Global Routing

Roughly plans wire paths without assigning specific tracks.
Identifies congested regions early.
Helps in timing and congestion analysis.
Uses routing tiles (GR grid) to estimate wire distribution.

2️⃣ Detailed Routing

Assigns exact metal tracks and vias to each net.
Ensures Design Rule Check (DRC) compliance.
Resolves shorts, spacing, and via issues.
Uses different metal layers for optimized routing.

4. Routing Constraints & Considerations

To ensure a clean and optimized layout, routing must follow certain constraints:

✅ 1. Layer Usage (Preferred Routing Directions)

Lower metal layers (M1–M3) → Used for local signal routing (short nets).
Middle metal layers (M4–M6) → Used for longer nets and clock signals.
Upper metal layers (M7 and above) → Used for power and global interconnects.
Preferred routing directions:
- Horizontal routing → Even layers (M2, M4, M6, etc.).
- Vertical routing → Odd layers (M1, M3, M5, etc.).

✅ 2. Via Minimization

Too many vias increase resistance and delay.
Optimize via placement to improve signal integrity.

✅ 3. Avoid Crosstalk & Noise

Maintain sufficient spacing between high-speed nets.
Use shielding techniques (placing VDD/VSS between sensitive signals).
Reduce parallel routing length of critical signals.

✅ 4. Power Routing (VDD/VSS)

Ensure thick power/ground rails to reduce IR drop.
Use multiple vias for strong power connections.
Place decoupling capacitors (decaps) to stabilize voltage.

✅ 5. DFM (Design for Manufacturability) Compliance

Follow foundry rules for metal density, via enclosure, and fill patterns.
Avoid acute angles and unnecessary bends in routing.

5. Routing Challenges

🚨 1. Congestion & Routing Blockages

Can cause timing violations and DRC errors.
Fixed by adjusting cell placement and macro positioning.

🚨 2. Timing Violations (Setup/Hold Violations)

Excessive wire delay can violate setup timing.
Buffer insertion or layer changes help reduce delay.

🚨 3. High Fanout Nets & Signal Integrity Issues

Clock and reset signals require special handling.
Shielding, buffering, and layer selection improve performance.

🚨 4. Crosstalk & Noise Issues

Avoid long parallel wires for critical signals.
Increase wire spacing and shielding to prevent interference.

🚨 5. Electromigration (EM) & IR Drop

High current paths cause metal degradation.
Use stronger metal layers and redundant vias to prevent failures.

6. Routing Verification & Analysis

After routing is completed, several checks are performed:

📌 Design Rule Check (DRC) → Ensure spacing, via, and width rules are followed.
📌 Static Timing Analysis (STA) → Verify setup/hold timing post-routing.
📌 IR Drop & EM Analysis → Check power integrity and current density.
📌 Parasitic Extraction (RC Extraction) → Generate SPEF file for timing closure.

7. Tools Used for Routing

Popular EDA tools for routing in VLSI:

🔹 Synopsys ICC2 (IC Compiler II)
🔹 Cadence Innovus
🔹 Mentor Graphics Olympus-SoC
🔹 Siemens Calibre (for DRC & LVS checks)

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ROUTING